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rohs compliant value added com pact flash series specification for industrial cf mar 8, 2011 version 1.0 apacer technology inc. 4 th fl., 75 hsin tai wu rd., sec.1, hsichih, new taipe i city, taiwan 221 tel: +886-2-2698-2888 fax: +886-2-2698-2889 www.apacer.com
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 1 ? 2011 apacer technology inc. rev. 1.0 features: compact flash association specification revision 3.0 standard interface C ata command set compatible C ata mode support for up to: pio mode-6 multiword dma mode-4 ultra dma mode-4 connector type C 50 pins female low power consumption (typical) C supply voltage: 3.3v & 5v C active mode: 80 ma/95 ma (3.3v/5.0v) C sleep mode: 700 a/900 a (3.3v/5.0v) performance ** C sustained read: 30 mb/sec C sustained write: standard: 5 mb/sec high speed: 15 mb/sec capacity C standard: 128, 256, 512 mb 1, 2, 16 gb C high speed: 256, 512 mb 1, 2, 4, 8 gb nand flash type: slc temperature ranges C operation: standard: 0c to 70c et*: -40c to 85c C storage: -40c to 100c flash management C intelligent endurance design advanced wear-leveling algorithms s.m.a.r.t. technology built-in hardware ecc enhanced data integrity C intelligent power failure recovery rohs compliant * extended temperature * * performance varies with flash configurations
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 2 ? 2011 apacer technology inc. rev. 1.0 table of contents 1. general description ............................. ................................................... ......... 3 1.1 p erformance -o ptimized c ontroller ................................................... ............................................ 3 1.1.1 power management unit (pmu).................. ................................................... .............................. 3 1.1.2 sram buffer .................................. ................................................... ............................................ 3 2. functional block ................................ ................................................... ............ 4 3. pin assignments ................................. ................................................... ............... 5 4. capacity specification .......................... ................................................... ........ 7 4.1 p erformance s pecification ................................................... ................................................... ........ 7 4.2 e nvironmental s pecifications ................................................... ................................................... .... 8 5. flash management ................................ ................................................... .......... 9 5.1 i ntelligent e ndurance d esign ................................................... ................................................... .... 9 5.1.1 advanced wear-leveling algorithms ............ ................................................... ............................... 9 5.1.2 s.m.a.r.t. technology........................ ................................................... ....................................... 9 5.1.3 built-in hardware ecc ........................ ................................................... ....................................... 9 5.1.4 enhanced data integrity ...................... ................................................... ....................................... 9 5.2 i ntelligent p ower f ailure r ecovery ................................................... .......................................... 10 6. software interface ............................. ................................................... ....... 11 6.1 c ommand s et ................................................... ................................................... .............................. 11 7. electrical specification ....................... ................................................... .... 13 7.1 dc c haracteristics ................................................... ................................................... ................... 14 7.2 ac c haracteristics ................................................... ................................................... ................... 15 7.2.1 attribute memory read timing specification ... ................................................... ....................... 16 7.2.2 configuration register (attribute memory) wri te specification ................................... ............... 17 7.2.3 common memory read timing specification ...... ................................................... ................... 18 7.2.4 common memory write timing specification ..... ................................................... .................... 19 7.2.5 i/o input (read) timing specification........ ................................................... .............................. 20 7.2.6 i/o output (write) timing specification ...... ................................................... ............................. 21 7.2.7 ultra dma mode data transfer input/output (re ad/write) timing................................... ......... 22 7.2.8 media side interface i/o timing specification s.................................................. ........................ 34 8. physical characteristics ....................... ................................................... .. 37 8.1 d imension ................................................... ................................................... .................................... 37 9. product ordering information ................... .............................................. 38 9.1 p roduct c ode d esignations ................................................... ................................................... ..... 38 9.2 v alid c ombinations ................................................... ................................................... .................... 39
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 3 ? 2011 apacer technology inc. rev. 1.0 1. general description apacers industrial compact flash card (cfc) offers the most reliable and high performance storage which is compatible with cf type i and type ii devi se. unlike the ordinary consumer compact flash cards, apacer industrial compact flash card provide s solid traceability to ensure all products hw/sw a re the same as you qualified. apacers cfc provides complete pcmcia - ata functio nality and compatibility. apacer s compact flash technology is designed for use in point of sale (po s) terminals, telecom, ip-stb, medical instruments, surveillance systems, industrial pcs and handheld a pplications. featuring technologies as advanced wear-leveling al gorithms, s.m.a.r.t, enhanced data integrity, built - in hardware ecc, and intelligent power failure reco very, apacers industrial compact flash card assures users of a versatile device on data storage . 1.1 performance-optimized controller the compact flash card controller translates standa rd cf signals into flash media data and control signals. 1.1.1 power management unit (pmu) the power management unit (pmu) controls the power consumption of the compact flash card controller. it reduces the power consumption of the compact fla sh card controller by putting circuitry not in operation into sleep mode. the pmu has zero wake-up latency. 1.1.2 sram buffer the compact flash card controller performs as an sr am buffer to optimize the hosts data transfer to and from the flash media.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 4 ? 2011 apacer technology inc. rev. 1.0 2. functional block the compact flash card (cfc) includes a controller and flash media, as well as the compact flash standard interface. figure 2-1 shows the functional block diagram. figure 2-1: functional block diagram flash media flash media flash media flash media flash array compact flash interface compact flash controller
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 5 ? 2011 apacer technology inc. rev. 1.0 3. pin assignments table 3-1 lists the pin assignments with respective signal names for the 50-pin configuration. a # s uffix indicates the active low signal. the pin type can b e input, output or input/output. table 3-1: pin assignments (1 of 2) memory card mode i/o card mode true ide mode pin no. signal name pin i/o type signal name pin i/o type signal name pin i/o type 1 gnd - gnd - gnd - 2 d3 i/o d3 i/o d3 i/o 3 d4 i/o d4 i/o d4 i/o 4 d5 i/o d5 i/o d5 i/o 5 d6 i/o d6 i/o d6 i/o 6 d7 i/o d7 i/o d7 i/o 7 #ce1 i #ce1 i #cs0 i 8 a10 i a10 i a10 1 i 9 #oe i #oe i #ata sel i 10 a9 i a9 i a9 1 i 11 a8 i a8 i a8 1 i 12 a7 i a7 i a7 1 i 13 vcc - vcc - vcc - 14 a6 i a6 i a6 1 i 15 a5 i a5 i a5 1 i 16 a4 i a4 i a4 1 i 17 a3 i a3 i a3 1 i 18 a2 i a2 i a2 i 19 a1 i a1 i a1 i 20 a0 i a0 i a0 i 21 d0 i/o d0 i/o d0 i/o 22 d1 i/o d1 i/o d1 i/o 23 d2 i/o d2 i/o d2 i/o 24 wp o #iois16 o #iocs16 o 25 #cd2 o #cd2 o #cd2 o 26 #cd1 o #cd1 o #cd1 o 27 d11 i/o d11 i/o d11 i/o 28 d12 i/o d12 i/o d12 i/o 29 d13 i/o d13 i/o d13 i/o 30 d14 i/o d14 i/o d14 i/o 31 d15 i/o d15 i/o d15 i/o 32 #ce2 i #ce2 i #cs1 i 33 #vs1 o #vs1 o #vs1 o 34 #iord i #iord i #iord i 35 #iowr i #iowr i #iowr i 36 #we i #we i #we i 37 rdy/-bsy o #ireq o intrq o 38 vcc - vcc - vcc - 39 #csel i #csel i #csel i 40 #vs2 o #vs2 o #vs2 o 41 reset i reset i #reset i
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 6 ? 2011 apacer technology inc. rev. 1.0 table 3-1: pin assignments (2 of 2) memory card mode i/o card mode true ide mode pin no. signal name pin i/o type signal name pin i/o type signal name pin i/o type 42 #wait o #wait o iordy o 43 #inpack o #inpack o dmarq 2 o 44 #reg i #reg i dmack 2 i 45 bvd2 o #spkr o #dasp o 46 bvd1 o #stschg o #pdiag o 47 d8 i/o d8 i/o d8 i/o 48 d9 i/o d9 i/o d9 i/o 49 d10 i/o d10 i/o d10 i/o 50 gnd - gnd - gnd - 1. the signal should be grounded by the host. 2. connection required when udma is in use.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 7 ? 2011 apacer technology inc. rev. 1.0 4. capacity specification capacity specification of the compact flash card se ries (cfc) is available as shown in table 4-1. it l ists the specific capacity and the default numbers of he ads, sectors and cylinders for each product line. table 4-1: capacity specifications capacity total bytes* cylinders heads sectors max lba 128 mb 128,450,560 980 8 32 250,880 256 mb 256,901,120 980 16 32 501,760 512 mb 512,483,328 993 16 63 1,000,944 1gb 1,024,966,656 1,986 16 63 2,001,888 2gb 2,048,901,120 3,970 16 63 4,001,760 4gb 4,110,188,544 7,964 16 63 8,027,712 8gb 8,195,604,480 15,880 16 63 16,007,040 16gb 16,391,208,960 16,383** 16 63 32,014,080 *display of total bytes varies from file systems. **cylinders, heads or sectors are not applicable fo r these capacities. only lba addressing applies 4.1 performance specification performances of the standard and high speed ata-fla sh disk are listed in table 4-2 and table 4-3. table 4-2: standard performance specifications capacity performance 128 mb / 256 mb 512 mb / 1 gb 2 gb 16 gb sustained read (mb/s) 15 20 20 sustained write (mb/s) 5 5 5 table 4-3: high speed performance specifications capacity performance 256 mb 512 mb 1 gb 2 gb 4 gb 8 gb sustained read (mb/s) 25 25 25 25 30 30 sustained write (mb/s) 5 5 5 5 10 15 note: performance varies from flash configurations.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 8 ? 2011 apacer technology inc. rev. 1.0 4.2 environmental specifications environmental specification of the compact flash ca rd series (cfc) which follows the mil-std-810f standards is available as shown in table 4-4. table 4-4: environmental specifications environment specification operation 0c to 70 (standard) ; -40c to 85 (extended temperature) temperature storage -40 to 100 humidity 5% to 95% rh (non-condensing) vibration (non-operation) sine wave: 10~2000hz, 15g (x, y, z axes) shock (non-operation) half sine wave, peak accelera tion 50 g, 11 ms (x, y, z ; all 6 axes)
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 9 ? 2011 apacer technology inc. rev. 1.0 5. flash management 5.1 intelligent endurance design 5.1.1 advanced wear-leveling algorithms the nand flash devices are limited by a certain num ber of write cycles. when using a file system, frequent file table updates is mandatory. if some a rea on the flash wears out faster than others, it w ould significantly reduce the lifetime of the whole devi ce, even if the erase counts of others are far from the write cycle limit. thus, if the write cycles can be distributed evenly across the media, the lifetime of the media can be prolonged significantly. the scheme is achieved both via buffer management and apacer- specific advanced wear leveling to ensure that the lifetime of the flash media can be increased, and t he disk access performance is optimized as well. 5.1.2 s.m.a.r.t. technology s.m.a.r.t. is an acronym for self-monitoring, analy sis and reporting technology, an open standard allowing disk drives to automatically monitor their own health and report potential problems. it prote cts the user from unscheduled downtime by monitoring and st oring critical drive performance and calibration parameters. ideally, this should allow taking proac tive actions to prevent impending drive failure. ap acer smart feature adopts the standard smart command b0h to read data from the drive. when the apacer smart utility running on the host, it analyzes and reports the disk status to the host before the devi ce is in critical condition. 5.1.3 built-in hardware ecc the ata-disk module uses bch error detection code ( edc) and error correction code (ecc) algorithms which correct up to eight random single- bit errors for each 512-byte block of data. high performance is fulfilled through hardware-based err or detection and correction. 5.1.4 enhanced data integrity the properties of nand flash memory make it ideal f or applications that require high integrity while operating in challenging environments. the integrit y of data to nand flash memory is generally maintained through ecc algorithms and bad block man agement. flash controllers can support up to 8 bits ecc capability for accuracy of data transactio ns, and bad block management is a preventive mechanism from loss of data by retiring unusable me dia blocks and relocating the data to the other blo cks, along with the integration of advanced wear levelin g algorithms, so that the lifespan of device can be expanded.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 10 ? 2011 apacer technology inc. rev. 1.0 5.2 intelligent power failure recovery the low power detection on the controller initiates cached data saving before the power supply to the device is too low. this feature prevents the device from crash and ensures data integrity during an unexpected blackout. once power was failure before cached data writing back into flash, data in the cache will lost. the next time the power is on, the controller will check these fragmented data segmen t, and, if necessary, replace them with old data kept in flash until programmed successfully.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 11 ? 2011 apacer technology inc. rev. 1.0 6. software interface 6.1 command set table 6-1 summarizes the command set with the parag raphs that follow describing the individual commands and the task file for each. table 6-1: command set (1 of 2) command code fr 1 sc 2 sn 3 cy 4 dh 5 lba 6 check-power-mode e5h or 98h - - - - d 8 - execute-drive-diagnostic 90h - - - - d - erase sector(s) c0h - y y y y y flush-cache e7h - - - - d - format track 50h - y 7 - y y 8 y identify-drive ech - - - - d - idle e3h or 97h - y - - d - idle-immediate e1h or 95h - - - - d - initialize-drive-parameters 91h - y - - y - nop 00h - - - - d - read-buffer e4h - - - - d - read-dma c8h or c9h - y y y y y read-multiple c4h - y y y y y read-sector(s) 20h or 21h - y y y y y read-verify-sector(s) 40h or 41h - y y y y y recalibrate 1xh - - - - d - request-sense 03h - - - - d - seek 7xh - - y y y y set-features efh y 7 - - - d -
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 12 ? 2011 apacer technology inc. rev. 1.0 table 6-1: command set (2 of 2) command code fr 1 sc 2 sn 3 cy 4 dh 5 lba 6 smart b0h y y y y d set-multiple-mode c6h - y - - d - set-sleep-mode e6h or 99h - - - - d - standby e2h or 96h - - - - d - standby-lmmediate e0h or 94h - - - - d - translate-sector 87h - y y y y y write-buffer e8h - - - - d - write-dma cah or cbh - y y y y y write-multiple c5h - y y y y y write-multiple-without-erase cdh - y y y y y write-sector(s) 30h or 31h - y y y y y write-sector-without-erase 38h - y y y y y write-verify 3ch - y y y y y 1. fr - features register 2. sc - sector count register 3. sn - sector number register 4. cy - cylinder registers 5. dh - drive/head register 6. lba - logical block address mode supported (see co mmand descriptions for use) 7. y - the register contains a valid parameter for th is command 8. for the drive/head register: y means both the cfc and head parameters are used d means only the cfc parameter is valid and not the head parameter
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 13 ? 2011 apacer technology inc. rev. 1.0 7. electrical specification caution: absolute maximum stress ratings C applied conditions greater than those listed under absolute maximum stress ratings may cause permane nt damage to the device. this is a stress rating only and functional operation of the device at thes e conditions or conditions greater than those defin ed in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability. table 7-1: operating range range ambient temperature 3.3v 5v standard 0c to +70c extended temperature -40c to +85c 3.135-3.465v 4.75-5.25v table 7-2: absolute maximum power pin stress ratings parameter symbol conditions input power v dd -0.3v min. to 6.5v max. voltage on any pin except v dd with respect to gnd v -0.5v min. to vdd + 0.5v max . table 7-3: recommended system power-up timing symbol parameter typical maximum units t pu-ready 1 power-up to ready operation 200 1000 ms t pu-write 1 power-up to write operation 200 1000 ms 1. this parameter is measured only for initial qual ification and after a design or process change that could affect this parameter.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 14 ? 2011 apacer technology inc. rev. 1.0 7.1 dc characteristics table 7-4: dc characteristics symbol type parameter min max units conditions v ih1 v il1 i1 input voltage 2.0v 0.8v v v ddq =v ddq max v ddq =v ddq min i il1 i1z input leakage current -10 10 a v in =gnd to v ddq v ddq = v ddq max i u1 i1u input pull-up current -110 -1 a v out =gnd, v ddq = v ddq max v t+2 v t-2 i2 input voltage schmitt trigger 0.8 2.0 v v ddq =v ddq max v ddq =v ddq min i il2 i2z input leakage current -10 10 a v in =gnd to v ddq v ddq = v ddq max i u2 i2u input pull-up current -110 -1 a v out =gnd, v ddq = v ddq max v oh1 v ol1 output voltage 2.4 0.4 v i oh1 =i oh1 min i ol1 =i ol1 max i oh1 output current -4 ma v ddq =v ddq min i ol1 o1 output current 4 ma v ddq =v ddq min v oh2 v ol2 output voltage 2.4 0.4 v i oh2 =i oh2 min i ol2 =i ol2 max i oh2 output current -6 ma v ddq =3.135v-3.465v i ol2 output current 6 ma v ddq =3.135v-3.465v i oh2 output current -8 ma v ddq =4.5v-5.5v i ol2 o2 output current 8 ma v ddq =4.5v-5.5v v oh6 v ol6 output voltage for dasp# pin 2.4 0.4 v i oh6 =i oh6 min i ol6 =i ol6 max i oh6 output current for dasp# pin -3 ma v ddq =3.135v-3.465v i ol6 output current for dasp# pin 8 ma v ddq =3.135v-3.465v i oh6 output current for dasp# pin -3 ma v ddq =4.5v-5.5v i ol6 o6 output current for dasp# pin 12 ma v ddq =4.5v-5.5v i dd 1,2 pwr power supply current (t a = 0c to +70c) 50 ma v dd =v dd max v ddq =v ddq max i dd 1,2 pwr power supply current (t a = -40c to +85c) 75 ma v dd =v dd max v ddq =v ddq max i sp pwr sleep/standby/idle current (t a = 0c to +70c) 75 a v dd =v dd max v ddq =v ddq max i sp pwr sleep/standby/idle current (t a = -40c to +85c) 200 a v dd =v dd max v ddq =v ddq max
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 15 ? 2011 apacer technology inc. rev. 1.0 7.2 ac characteristics figure 7-1: ac input/output reference waveforms ac test inputs are driven at viht (0.9 vdd) for a l ogic 1 and vilt (0.1 vdd) for a logic 0. measurement reference points for inputs and outputs are vit (0.5 vdd) and vot (0.5 vdd). input rise and fall times (10% ? 90%) are <10 ns. note: v it - v input test v ot - v output test v iht - v input high test v ilt - v input low test
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 16 ? 2011 apacer technology inc. rev. 1.0 7.2.1 attribute memory read timing specification the attribute memory access time is defined as 100 ns. detailed timing specifications are shown in the table below. table 7-5: attribute memory read timing specification speed version 100 ns item symbol ieee symbol min* max* units read cycle time t c(r) tavav 100 ns address access time t a(a) tavqv 100 ns card enable access time t a(ce) telqv 100 ns output enable access time t a(oe) tglqv 50 ns output disable time from ce# t dis(ce) tehqz 50 ns output disable time from oe# t dis(oe) tghqz 50 ns address setup time t su(a) tavgl 10 ns output enable time from ce# t en(ce) telqnz 5 ns output enable time from oe# t en(oe) tglqnz 5 ns data valid from address change t v(a) taxqz 0 ns *d out signifies data provided by the compact flash card to the system. the ce# signal or both the oe# signa l and the we# signal must be de-asserted between consecutive cycle opera tions. all ac specifications are guaranteed by desi gn. figure 7-2: attribute memory read timing diagram
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 17 ? 2011 apacer technology inc. rev. 1.0 7.2.2 configuration register (attribute memory) wri te specification the card configuration write access time is defined as 100 ns. detailed timing specifications are show n in the table below. table 7-6: configuration register (attribute memory) write tim ing speed version 100 ns item symbol ieee symbol min* max* units write cycle time t c(w) tavav 100 ns write pulse width t w(we) twlwh 60 ns address setup time t su(a) tavwl 10 ns write recover time t rec(we) twmax 15 ns data setup time for we t su(dwe#h) tdvwh 40 ns data hold time t h(d) twmdx 15 ns *d in signifies data provided by the system to the compa ct flash card. all ac specifications are guaranteed by design. figure 7-3: configuration register (attribute memory) write ti ming diagram
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 18 ? 2011 apacer technology inc. rev. 1.0 7.2.3 common memory read timing specification table 7-7: common memory read timing item symbol ieee symbol min* max* units output enable access time t a(oe) tglqv 50 ns output disable time from oe t dis(oe) tghqz 50 ns address setup time t su(a) tavgl 10 ns address hold time t rec(we) tghax 15 ns ce setup before oe t su(ce) telgl 0 ns ce hold following oe t h(ce) tgheh 15 ns *all ac specifications are guaranteed by design. figure 7-4: common memory read timing diagram
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 19 ? 2011 apacer technology inc. rev. 1.0 7.2.4 common memory write timing specification table 7-8: common memory write timing item symbol ieee symbol min* max* units data setup before we t su(dwe#h) tdvwh 40 ns data hold following we t h(d) twmdx 15 ns we pulse width t w(we) twlwh 60 ns address setup time t su(a) tavwl 10 ns ce setup before we t su(ce) telwl 0 ns write recovery time t rec(we) twmax 15 ns address hold time t h(a) tghax 15 ns ce hold following we t h(ce) tgheh 15 ns *all ac specifications are guaranteed by design. figure 7-5: common memory write timing diagram
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 20 ? 2011 apacer technology inc. rev. 1.0 7.2.5 i/o input (read) timing specification table 7-9: i/o read timing item symbol ieee symbol min* max* units data delay after iord t d(iord) tlglqv 100 ns data hold following iord t h(iord) tlghqx 0 ns iord width time t w(iord) tlgligh 165 ns address setup before iord t sua(iord) tavigl 70 ns address hold following iord t ha(iord) tlghax 20 ns ce setup before iord t suce(iord) teligl 5 ns ce hold following iord t hce(iord) tlgheh 20 ns reg setup before iord t sureg(iord) trgligl 5 ns reg hold following iord t hreg(iord) tlghrgh 0 ns inpack delay falling from iord t dfinpack(iord) tlglial 0 45 ns inpack delay rising from iord t drinpack(iord) tlghiah 45 ns iois16 delay falling from address t dfiois16(ard) tavisl 35 ns iois16 delay rising from address t driois16(adr) tavish 35 ns *all ac specifications are guaranteed by design. note: the maximum load on Cinpack and iois16# is 1 lsttl with 50pf total load. figure 7-6: i/o read timing diagram
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 21 ? 2011 apacer technology inc. rev. 1.0 7.2.6 i/o output (write) timing specification table 7-10: i/o write timing item symbol ieee symbol min* max* units data setup before iowr t su(iowr) tdviwh 60 ns data hold following iowr t h(iowr) tlwhdx 30 ns iowr width time t w(iowr) tlwliwh 165 ns address setup before iowr t sua(iowr) taviwl 70 ns address hold following iowr t ha(iowr) tlwhax 20 ns ce setup before iowr t suce(iowr) teliwl 5 ns ce hold following iowr t hce(iowr) tlwheh 20 ns reg setup before iowr t sureg(iowr) trgliwl 5 ns reg hold following iowr t hreg(iowr) tlwhrgh 0 ns iois16 delay falling from address t dfiois16(ard) tavisl 35 ns iois16 delay rising from address t driois16(adr) tavish 35 ns *all ac specifications are guaranteed by design. note: the maximum load on Cinpack and iois16# is 1 lsttl with 50pf total load. figure 7-7: i/o write timing diagram
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 22 ? 2011 apacer technology inc. rev. 1.0 7.2.7 ultra dma mode data transfer input/output (re ad/write) timing table 7-11: ultra dma data burst timing specifications 1 mode 4 name descriptions min max unit measurement location 2 t 2cyctyp typical sustained average two cycle time 60 ns sen der t cyc cycle time allowing for asymmetry and clock variations (from strobe edge to strobe edge) 25 ns note 3 t 2cyc two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of strobe) 57 ns sender t ds data setup time at recipient (from data valid until strobe edge) 4,5 5.0 ns recipient t dh data hold time at recipient (from strobe edge until data becomes invalid) 1,2 5.0 ns recipient t dvs data valid setup time for sender (from data valid until strobe edge) 6 6.0 ns sender t dvh data valid hold time at sender (from strobe edge until data becomes invalid) 3 6.0 ns sender t cs crc word setup time at device 1 5.0 ns device t ch crc word hold time at device 1 5.0 ns device t cvs crc word valid setup time at host (from crc valid until dmack negation) 3 6.7 ns host t cvh crc word valid hold time at sender (from dmack negation until crc becomes invalid) 3 6.2 ns host t zfs time from strobe output released-to-driving until the first transition of critical timing 0 ns device t dzfs time from data output released-to-driving until the first transition of critical timing 6.7 ns sender t fs first strobe time (for device to first negate dstrobe from stop during a data in burst) 120 ns device t li limited interlock time 7 0 100 ns note 8 t mli interlock time with minimum 4 20 ns host t ui unlimited interlock time 4 0 ns host t az maximum time allowed for output drivers to release (from asserted to negated) 10 ns note 9 t zah minimum delay time required for output 20 ns host t zad drivers to assert or negate (from released) 0 ns d evice t env envelope time (from dmack# to stop and hdmardy# during data in burst initiation and from dmack to stop during data our burst initiation) 20 55 ns host t rfs ready-to-final strobe time (no strobe edge are sent this long after negation of dmardy) 60 ns sender t rp ready-to-pause time (recipient waits to pause until after negating dmardy) 100 ns recipient t iordyz maximum time before releasing iordy 20 ns device t ziordy minimum time before driving iordy 10 0 ns device t ack 20 ns host t ss 50 ns sender
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 23 ? 2011 apacer technology inc. rev. 1.0 1. all timing measurement switching points (low-to- high and high-to-low) are taken at 1.5v. 2. all signal transitions for a timing parameter ar e measured at the connector specified in the measur ement location column. for example, in the case of trfs, both strobe and dmard y transitions are measured at the sender connector. 3. the parameter tcyc is measured at the recipient s connector farthest from the sender. 4. 80-conductor cabling is required in order to mee t sup (tds, tcs) and hold (tdh, tch) times in modes greater than two. 5. the parameters tds and tdh for mode 5 are define d for a recipient at the end of the cable only in a configuration with a single device located at the end of the cable. this could result in the minimum values for tds and tdh for mo de 5 at the middle connector being 3.0 and 3.9 ns respectively. 6. timing for tdvs, tdvh, tcvs, and tcvh are met fo r lumped capacitive loads of 15 and 50 pf at the co nnector where the data and strobe signals have the same capacitive load va lue. due to reflections on the cable, these timing measurements are not valid in a normally functioning system. 7. the parameters tui, tmli, and tli indicate sende r-to-recipient or recipient-to-sender interlocks. f or example, one agent (either sender or recipient) is waiting for the oth er agent to respond with a signal before proceeding ; tui is an unlimited interlock that has no maximum time value, tmli is a limited time-out that has a defined minimum, and t li is a limited time-out that has a defined maximum. 8. the parameter tli is measured at the connector o f the sender or recipient that is responding to an incoming transition from the recipient or sender respectively. both the incoming signal and the outgoing response are measured at t he same connector. 9. the parameter taz is measured at the connector o f the sender or recipient that is driving the bus b ut must release the bus that allow for a bus turnaround. 10. for all modes the parameter tziordy may be grea ter than tenv because the host has a pull-on iordy giving it a known state when released.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 24 ? 2011 apacer technology inc. rev. 1.0 table 7-12: ultra dma sender and recipient ic timing specificat ions 1 mode 4 name descriptions min max unit t dsic recipient ic data setup time (from data valid until strobe edge) 2 4.8 ns t dhic recipient ic data hold time (from strobe edge until data becomes invalid) 1 4.8 ns t dvsic sender ic data valid setup time (from data valid un til strobe edge) 3 9.5 ns t dvhic 9.0 ns 1. all timing measurement switching point (low-to-h igh and high-to-low) 2. the correct data value is captured by the recipi ent given input data with a slew rate of 0.4 v/ns r ising and falling and the input strobe with a slew rate of 0.4 v/ns rising and fall ing at tdsic and tdhic timing (as measured through 1.5 v). 3. the parameters tdvsic and tdvhic are met for lum ped capacitive loads of 15 and 40 pf at the ic wher e all signals have the same capacitive load value. noise that may couple o nto the output signals from external sources has no t been included in these values. figure 7-8: initiating an ultra dma data-in burst notes: 1. the definitions for the diow-:stop, dior-:hdmard y-:hstrobe, and iordy:ddrardy-: dstrobe signal line s are not in effect until dmarq and dmack are asserted.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 25 ? 2011 apacer technology inc. rev. 1.0 figure 7-9: sustained ultra dma data-in burst notes: 1. dd(15:0) and dstrobe signals are shown at both t he host and the device to emphasize that cable sett ling time as well as cable propagation delay will not allow the data sig nals to be considered stable at the host until some time after they are driven by the device.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 26 ? 2011 apacer technology inc. rev. 1.0 figure 7-10: sustained ultra dma data-in burst notes: 1. the host may assert stop to request termination of the ultra dma burst no sooner than trp after hdm ardy# is negated. 2. after negating hdmardy#, the host may receive ze ro, one, two, or three more data words from the dev ice.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 27 ? 2011 apacer technology inc. rev. 1.0 figure 7-11: device terminating and ultra dma data-in burst notes: 1. the definitions for the stop, hdmardy, and dstro be signal lines are no longer in effect after dmarq and dmack are negated.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 28 ? 2011 apacer technology inc. rev. 1.0 figure 7-12: host terminating and ultra dma data-in burst notes: 1. the definitions for the stop, hdmardy, and dstro be signal lines are no longer in effect after dmarq and dmack are negated.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 29 ? 2011 apacer technology inc. rev. 1.0 figure 7-13: initiating an ultra dma data-out burst notes: 1. the definitions for the stop, ddmardy, and hstro be signal lines are no longer in effect after dmarq and dmack are negated.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 30 ? 2011 apacer technology inc. rev. 1.0 figure 7-14: sustained ultra dma data-out burst notes: 1. dd(15:0) and hstrobe signals are shown at both t he host and the device to emphasize that cable sett ling time as well as cable propagation delay will not allow the data sig nals to be considered stable at the host until some time after they are driven by the host.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 31 ? 2011 apacer technology inc. rev. 1.0 figure 7-15: device pausing and ultra dma data-out burst notes: 1. the host may negate dmarq to request termination of the ultra dma burst no sooner than trp after dd mardy# is negated. 2. after negating ddmardy#, the host may receive ze ro, one, two, or three more data words from the hos t.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 32 ? 2011 apacer technology inc. rev. 1.0 figure 7-16: host terminating and ultra dma data-out burst notes: 1. the definitions for the stop, ddmardy, and hstrobe signal lines are no longer in effect after dmarq an d dmack are negated.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 33 ? 2011 apacer technology inc. rev. 1.0 figure 7-17: device terminating and ultra dma data-out burst notes: 1. the definitions for the stop, ddmardy, and hstro be signal lines are no longer in effect after dmarq and dmack are negated.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 34 ? 2011 apacer technology inc. rev. 1.0 7.2.8 media side interface i/o timing specification s table 7-13: timing parameter symbol parameter min max units t cls fcle setup time 20 - ns t clh fcle hold time 40 - ns t cs fce# setup time 40 - ns t ch fce# hold time for command/data write cycle 40 - ns t chr fce# hold time for sequential read last cycle - 40 ns t wp fwe# pulse width 20 - ns t wh fwe# high hold time 20 - ns t wc write cycle time 40 - ns t als fale setup time 20 - ns t alh fale hold time 40 - ns t ds fad[15:0] setup time 20 - ns t dh fad[15:0] hold time 20 - ns t rp fre# pulse width 20 - ns t rr ready to fre# low 40 - ns t res fre# data setup access time 20 - ns t rc read cycle time 40 - ns t reh fre# high hold time 20 - ns t rhz fre# high to data hi-z 5 - ns note: all ac specifications are guaranteed by design.
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 35 ? 2011 apacer technology inc. rev. 1.0 figure 7-18: media command latch cycle figure 7-19: media access latch cycle
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 36 ? 2011 apacer technology inc. rev. 1.0 figure 7-20: media data loading latch cycle figure 7-21: media data read cycle
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 37 ? 2011 apacer technology inc. rev. 1.0 8. physical characteristics 8.1 dimension t able 8-1: type i cfc physical specification length: 36.40 +/- 0.15mm (1.433+/- 0.06 in.) width: 42.80 +/- 0.10mm (1.685+/- 0.04 in.) thickness (including label area): 3.3mm+/-0.10mm (0.130+/-0.04in.) f igure 8-1: physical dimension unit: mm
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 38 ? 2011 apacer technology inc. rev. 1.0 9. product ordering information 9.1 product code designations a p C c f x x x x e 3 x r C xxxxxxk cfc type capacity: 128m: 128mb 256m: 256mb 512m: 512mb 001g: 1gb 002g: 2gb 004g: 4gb 008g: 8gb 016g: 16gb model name apacer product code configuration e: standard f: high speed specification nr: non-removable setting ndnr: non-dma + non-removable etnr: ext. temp. + non-removable etndnr: ext. temp + non-dma + non-removable k: value added rohs compliant controller type
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 39 ? 2011 apacer technology inc. rev. 1.0 9.2 valid combinations standard temperature non-removable standard high speed capacity model number capacity model number 128mb ap-cf128me3er-nrk 256mb ap-cf256me3fr-nrk 256mb ap-cf256me3er-nrk 512mb ap-cf512me3fr-nrk 512mb ap-cf512me3er-nrk 1gb ap-cf001ge3fr-nrk 1gb ap-cf001ge3er-nrk 2gb ap-cf002ge3fr-nrk 2gb ap-cf002ge3er-nrk 4gb ap-cf004ge3fr-nrk 16gb ap-cf016ge3er-nrk 8gb ap-cf008ge3fr-nrk non-dma & non-removable standard high speed capacity model number capacity model number 128mb ap-cf128me3er-ndnrk 256mb ap-cf256me3fr-ndnrk 256mb ap-cf256me3er-ndnrk 512mb ap-cf512me3fr-ndnrk 512mb ap-cf512me3er-ndnrk 1gb ap-cf001ge3fr-ndnrk 1gb ap-cf001ge3er-ndnrk 2gb ap-cf002ge3fr-ndnrk 2gb ap-cf002ge3er-ndnrk 4gb ap-cf004ge3fr-ndnrk 16gb ap-cf016ge3er-ndnrk 8gb ap-cf008ge3fr-ndnrk
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 40 ? 2011 apacer technology inc. rev. 1.0 extended temperature non-removable standard high speed capacity model number capacity model number 128mb ap-cf128me3er-etnrk 256mb ap-cf256me3fr-etnrk 256mb ap-cf256me3er-etnrk 512mb ap-cf512me3fr-etnrk 512mb ap-cf512me3er-etnrk 1gb ap-cf001ge3fr-etnrk 1gb ap-cf001ge3er-etnrk 2gb ap-cf002ge3fr-etnrk 2gb ap-cf002ge3er-etnrk 4gb ap-cf004ge3fr-etnrk 16gb ap-cf016ge3er-etnrk 8gb ap-cf008ge3fr-etnrk non-dma & non-removable standard high speed capacity model number capacity model number 128mb ap-cf128me3er-etndnrk 256mb ap-cf256me3fr-etndnrk 256mb ap-cf256me3er-etndnrk 512mb ap-cf512me3fr-etndnrk 512mb ap-cf512me3er-etndnrk 1gb ap-cf001ge3fr-etndnrk 1gb ap-cf001ge3er-etndnrk 2gb ap-cf002ge3fr-etndnrk 2gb ap-cf002ge3er-etndnrk 4gb ap-cf004ge3fr-etndnrk 16gb ap-cf016ge3er-etndnrk 8gb AP-CF008GE3FR-ETNDNRK
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 41 ? 2011 apacer technology inc. rev. 1.0 revision history revision description date 1.0 official release mar 8, 2011
value added compact flash series ap-cfxxxxe3xr-xxxxxxk 42 ? 2011 apacer technology inc. rev. 1.0 global presence taiwan (headquarters) apacer technology inc. 4 th fl, 75 xintai 5 th rd., sec.1 hsichih, new taipei city taiwan 221 r.o.c. tel: +886-2-2698-2888 fax: +886-2-2698-2889 amtsales@apacer.com u.s.a. apacer memory america, inc. 386 fairview way, suite102, milpitas, ca 95035 tel: 1-408-518-8699 fax: 1-408-935-9611 sa@apacerus.com japan apacer technology corp. 5f, matsura bldg., shiba, minato-ku tokyo, 105-0014, japan tel: 81-3-5419-2668 fax: 81-3-5419-0018 jpservices@apacer.com europe apacer technology b.v. azi?laan 22, 5232 ba 's-hertogenbosch, the netherlands tel: 31-73-645-9620 fax: 31-73-645-9629 sales@apacer.nl china apacer electronic (shanghai) co., ltd 1301, no.251,xiaomuqiao road, shanghai, 200032, china tel: 86-21-5529-0222 fax: 86-21-5206-6939 sales@apacer.com.cn india apacer technologies pvt ltd, #1064, 1st floor, 7th a main, 3rd block koramangala, bangalore C 560 034 tel: +91 80 4152 9061/62/63 fax: +91 80 4170 0215 sales_india@apacer.com
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